1. Technical Field
The present disclosure relates in general to integrated circuit processing, and more particularly to static timing analysis of an integrated circuit with respect to processing parameters.
2. Background Art
Corner-based static timing has long been the bedrock technology for timing verification of integrated circuits. Timing of integrated circuits with the same timing design may vary due to processing variations. A corner refers to a set of parameters/conditions (hereinafter “parameter”) that cause variations in the static timing. Processing variations can be classified into two groups: global variations and local variations. Conventionally, global variations, also referred to as chip-to-chip variations, are accommodated by a multi-corner timing. Specifically, every global variation is set to its three-standard deviation (3 sigma) extreme corners, one corner providing the fastest signal propagating checked in the fast chip timing analysis and another corner providing the slowest signal propagation checked in the slow chip timing analysis. Local variations, also referred to as on-chip variations, are modeled by means of creating timing skew by making early path latency smaller and late path latency larger. This is referred to as an early/late split. The early/late split is often introduced by “derating coefficients”.